1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to process and structure for the reduction of channeling during the implantation of source and drain regions during the formation of MOS integrated circuit structures on a semiconductor substrate.
2. Description of the Related Art
In the formation of MOS devices in integrated circuit structures on a semiconductor substrate, a gate oxide layer and a polysilicon layer are formed over a semiconductor substrate, such as a single crystal silicon substrate, and the polysilicon layer is patterned to form the polysilicon gate electrode of the MOS structure, with the gate oxide beneath the polysilicon separating the polysilicon gate electrode from the underlying channel region in the semiconductor substrate.
During the patterning of the polysilicon layer to form the gate electrode, portions of the underlying substrate adjacent the gate electrode are exposed where source and drain regions will be formed in the substrate adjacent the aforementioned channel region. After this patterning step, the entire structure is implanted with a dopant, e.g., boron, phosphorus, or arsenic, depending upon whether P type or N type doping is desired, to form the source and drain regions in the exposed substrate portions. During this implanting step, channeling of the dopant ions through the polysilicon gate electrode into the underlying channel region of the substrate may occur.
After deposition of the polysilicon layer, and doping it to form highly conductive polysilicon, an anneal cycle is carried out during which the grain size of the polysilicon increases, thus making it easier for some of the subsequently implanted dopant ions to channel through the polysilicon gate electrode into the underlying channel region in the substrate. Such implantation of the channel region is undesirable, for example, because it results in an erratic threshold voltage in the resultant MOS device. This poses severe limitations on the fabrication of MOS transistors.
In the past, this problem of channeling through the polysilicon gate electrode was solved by limiting the energy of the ion implantation of the subsequently implanted source/drain dopant so that the implanted dopant did not penetrate through the polysilicon gate electrode to the underlying channel region of the substrate.
When the thickness of the polysilicon gate electrode ranged from about 0.35 to 0.4 micrometers (.mu.m), i.e., 3500-4000 Angstroms, such a limiting of the source/drain dopant implantation energy was sufficient to remedy the problem. However, as the lateral device and line dimensions shrink in an integrated circuit structure, i.e. shrinkage of line width, so should the thicknesses of the lines and devices. However, attempts to shrink the thickness of the polysilicon gate electrode from the aforementioned 0.35-0.4 .mu.m thickness down to about 0.2 .mu.m results in undesirable implantation of the underlying channel region of the MOS device (even when the ion implantation energy is limited) through channeling of the dopant through the polysilicon gate electrode, because of such thinning of the polysilicon gate electrode thickness.
It would, therefore, be highly desirable to provide a process and structure which would inhibit channeling, through the polysilicon gate electrode, of dopant used to form the implanted source and drain regions of a semiconductor substrate, while still permitting the use of polysilicon gate electrodes having a thickness of less than 0.35 .mu.m, i.e., down to as thin as about 0.2 .mu.m.